1. Field of the Invention
The present invention relates to a switching system, and more particularly to a time management method for a switching system.
2. Description of the Conventional Art
Generally, time of a switching system must be synchronized with International Standard Time. However, since the switching system has no synchronizing apparatus, an indirect way is applied. For example, a referential time (TDC: year, month, day, time, minute and second) of the switching system is set in accordance with a hardware HW time supplied from a time generating apparatus, a software SW time which is maintained by a real time clock (RTC) of each processor and a user time supplied by an operator.
FIG. 1 illustrates a time management apparatus for the conventional switching system.
As shown therein, the time management apparatus for the conventional switching system includes an OMP (operating and maintenance processor) 100, an OMDC (operating and maintenance device controller) 200, an HW time device 300, and an MP (maintenance processor) 400.
Particularly, the OMP 100 which operates and maintains the switching system determines a system time and periodically checks the time concordance using an SCM (system clock management), a system time management master. Also, the OMP 100 distributes the system time which has been determined in the system time determining process and periodical time concordance checking process to the MP 400.
The OMDC 200 controlling and checking an HW time is connected with the OMP 100 through an IPC (inter processor communication) 10 and connected with the HW time device 300 through a DA (data access)-bus, accesses the HW time device 300 in accordance with an HW time request of the OMP 100, and reports the accessed HW time to the OMP 100.
The MP 400 consisting of an SNP (switching network processor) 40 and a plurality of SSPs (switching subsystem processors) 40-1xcx9c40-n is connected with the OMP 100 through IPC links 11xcx9c17. The description of the connection and operation of the IPC links will be omitted since it is irrelevant to the time management operation. The SSPs 40-1xcx9c40-n carry out user/trunk matching and time switching operations and the SNP 40 performs space switching of outputs of the SSPs 40-1xcx9c40-n and supplies the resultant outputs to a plurality of highways. Here, the number of SSPs 40-1xcx9c40-n connected with the SNP 40 can be up to 32 at its maximum in consideration of the highways. In addition, the SNP 40 and the SSPs 40-1xcx9c40-n are respectively provided with the SCM block of itself and set its own SW time in accordance with system time which is distributed by the OMP 100.
With reference to FIG. 1, the operation of the time management apparatus for the conventional switching system will now be described.
In the initial start (or restart) of the system, the SCM block of the OMP 100 requests the OMDC 200 through the IPC line 10 to send the HW time, and the OMDC 200 access the HW time device 300 through the DA-bus and reports the HW time to the OMP 100. When receiving the HW time from the OMDC 200, the SCM block of the OMP 100 sets the HW time as an initial system time and then distributes the initial system time to the MP 400 through the IPCs 11xcx9c17. However, if not receiving the HW time from the OMDC 200 due to defect of the HW time device 300, the SCM block of the OMP 100 sets a predetermined time which is set by a user as the initial system time and distributes the initial system time to the MP 400. Accordingly, the SCM blocks of the SNP 40 and the SSPs 40-1xcx9c40-n of the MP 400 respectively set the time (SW time) of its own in accordance with the initial system time which is distributed from the OMP 100. When the initial system time is set, the SCM block of the OMP 100 periodically resets the system time with reference to the HW time, the OMP time and the MP time in order, and distributes the reset system time to the MP 400, so that the times of the switching system concur.
Now, the time management method of the conventional switching system will be described with reference to FIG. 2.
FIG. 2 is a flowchart illustrating setting of an initial system time in the system initial start (or restart). The system time management master is the SCM block of the OMP 100. The SCM block request the HW time to the OMDC 200 when starting the system, the OMP 100 or the SCM block thereof, and registers a time-out signal of 5 seconds with an OS (operation system) (S1, S2). When receiving the HW time from the OMDC 200 before the time-out signal is inputted, the SCM block determines whether the received HW time has a normal time value (S3, S4) by checking time data (year, month, day, time, minute, second) of the HW time. For example, the normality of the HW time is determined by checking whether the time data is under 24 and minute and second data are respectively under 60. When the HW time has the normal time value, the SCM block sets the received HW time as the initial system time (the initial system time=the HW time).
Meanwhile, when if the HW time is not outputted from the OMDC 200 until the time-out signal is supplied from the OS (S6) or the HW time has an abnormal time value in the step S4, the SCM block outputs an alarm message and then sets the time set by the user as the initial system time (the initial system time=the user time) (S7). Once the initial system time is set, the SCM block distributes the initial system time to the MP 400 (S8), and the SNP 40 and SSPs 40-1xcx9c40-n of the MP 400 respectively set the time of itself (SW time) as the initial system time and process all the functions, for example, metering, related with the time on the basis of the SW time. Further, the SCM block registers a cycle signal Cycle_sig of a 1 minute cycle with the OS to periodically check the time concordance (S9).
FIGS. 3A through 3D are flowcharts illustrating checking of the time concordance with reference to the HW time, the OMP time and the MP time.
As shown therein, when the initial system time is set, the SCM block of the OMP 100 operates (is interrupted) in a 1 minute cycle in accordance with the cycle signal Cycle_sig and thus resets the system time referring to the HW time, the SW time of the OMP 100 or the SW time of the MP 400. That is, the SCM block compares in order the HW time with the OMP time, the HW time with the MP time, the OMP time with the MP time and the MP times with each other, thereby determining the system time, because the reliability of the time is in order of the HW time, the OMP time and the MP time. Further, when the above processes are all failed, the OMP time is set as the system time. When the system time is reset, the SCM block distributes the reset system time to the MP 400, and thus periodically checks the time concordance by making the times of the dispersed processors concur with each other, that is, the SNP 40 and the SSPs 40-1xcx9c40-n of the MP 400.
More specifically, FIG. 3A is a flowchart illustrating the operation of comparing the HW time with the OMP time and thus determining the system time. As shown therein, The SCM block of the OMP 100 which operates in the 1 minute cycle in accordance with the cycle signal Cycle_sig requests the HW time to the OMDC 200 and registers the time-out signal with the OS (S10, S11). When receiving the HW time from the OMDC 200, the SCM block stores the received HW time and checks whether the HW time has the normal time value (S13). When the HW time is normal, the SCM block computes the time difference between the time (the OMP time) maintained by the RTC of itself and the HW time (S13, S14) and determines whether the computed time difference is a predetermined value (3 seconds) and below (S15). If the time difference is the 3 seconds and below, the SCM block resets the corresponding HW time as the system time (the system time=the HW time) (S16) and distributes the corresponding system time to the MP 400 (S17). As a result, each of the SNP 40 and the SSPs 40-1xcx9c40-n of the MP 400 unconditionally synchronizes the time thereof with the reset system time, so that the times of the dispersed processors concur with each other. However, when the SCM block receives the time-out signal without receiving the HW time (S18) or when the time difference is greater than the predetermined value (3 seconds) in the step S15, the SCM block proceeds to a step S21, which will be later described, and compares the HW time with the time of the MP 400. FIG. 3B is a flowchart illustrating the operation which compares the HW time with the MP time and thus determining the system time. As shown therein, the SCM block of the OMP 100 requests the SW time to the MP 400 and registers the time-out signal with the OS (S21, S22). When receiving the SW time from the SCM of each of the SNP 40 and the SSPs 40-1xcx9c40-n, the SCM block of the OMP 100 stores the received SW times and checks whether the SCM already received the HW time in the above-mentioned step S12 of FIG. 3A (S24). When having received the HW time, the SCM block computes the time difference between the HW time and the MP time, for example, the SNP 40 (S25), and checks whether the computed time difference is the predetermined value (3 seconds) and below. As a result, if the time difference between the HW time and the MP time is the 3 seconds and below, the SCM block increases a count value same_cnt by xe2x80x9c1xe2x80x9d and returns to the step S23 (S27). Repeatedly performing the above operation, the SCM block sequentially compares the HW time with each time of the SSPs 40-1xcx9c40-n, until the time-out signal is supplied from the OS. When receiving the time-out signal after 5 seconds (S28), the SCM block compares the count value same_cnt with a predetermined value (3 times) (S29). Here, if the count value same_cnt is the same as the predetermined value or more, that is, if a case where the time difference is the 3 seconds and below is generated at least 3 consecutive times, the SCM block resets the system time as the HW time and distributes the reset system time to the MP 400 (S30, S31). However, if the HW time is not received in the step (S12) of FIG. 3A or when the counter value same_cnt is less than the predetermined value, the SCM block proceeds to a step S32, which will be later described, and compares the OMP time with the MP time.
FIG. 3C is a flowchart illustrating the operation which compares the OMP time with the MP time and thus determines the system time. As shown therein, the SCM block requests the SW time to the MP 400 and registers the time-out signal with the OS (S32, S33). When the SCMs provided in the SNP 40 and the SSPs 40-1xcx9c40-n of the MP 400 respectively receive the SW times, the SCMs stores the MP time therein (S34) and computes the difference between the OMP time and the MP time (S35). After computing the time difference between the OMP time and the MP time, the SCM block increases the count value same_cnt by xe2x80x981xe2x80x99 when the computed time difference is the predetermined value (3 seconds) and below, and returns to the step S34 (S37). Then the SCM block repeatedly performs the above process, for thereby comparing the MP time with the OMP time. Such a comparison is carried out until the SCM receives the time-out signal from the OS. When receiving the time-out signal (S38), the SCM block compares the count value same_cnt with a predetermined value (3 times) (S39). Here, if the count value same_cnt is greater than the predetermined value or more, the SCM block resets the system time as the OMP time and then distributes the reset system time to the MP 400 (S40, S41). However, if the SW time is not supplied from the MP until the time-out signal is inputted, or if the count value same_cnt is less than the predetermined value, the SCM block proceeds to a step S42, which will be later described, and compares the times of the MP 400.
FIG. 3D is a flowchart illustrating an operation for comparing the MP times and determining the system time. As shown therein, the SCM block requests the SW time to the MP 400 and registers the time-out signal with the OS (S42, S43). When receiving the SW times from the SNP 40 and the SSPs 40-1xcx9c40-n of the MP 400, the SCM block stores the SW times therein (S44) and computes the difference of the SW times from each other (S45). After computing the time difference, the SCM block increases the count value same_cnt by xe2x80x981xe2x80x99 when the computed time difference is a predetermined value (3 seconds) and below, and returns to the step S44 (S47). Then the SCM block repeatedly performs the above process, and when receiving the time-out signal (S48), the SCM block compares the count value same_cnt with a predetermined value (3 times) (S49). If the count value same_cnt is greater than the predetermined value, that is, when the case where the time difference is the 3 seconds and below is generated at least 3 consecutive times, the SCM block resets the system time as the OMP time and then distributes the reset system time to the MP 400 (S40, S41). As described above, the SCM block of the OMP 100 compares the HW time and the SW time of the OMP 100, or the SW times of the MP 400 every 1 minute, resets the system time and distributes the system time, thereby obtaining the time concordance of the switching system.
Generally, in a distribution processor environment, an internal communication (IPC) delay unavoidably occurs in the IPC among processors. However, in the conventional time management the time difference due to the IPC delay is not considered, but the time is managed through the simple comparison of the HW time, the OMP time and the MP time, which results in the time discordance with the actual time in the periodical time concordance check.
Further, in the conventional time management method, the system time always maintains the HW time as long as the HW time is received. However, since the conventional time management does not secure the reliability of the HW time, the system time and the times distributed to the processors can be erroneously set when the HW time is temporally changed.
In addition, since the conventional time management method performs the time setting and correcting by unconditionally making the MP time concur with the system time, if the present MP time is faster than the system time, the MP time instantaneously or for a certain period passes backward, while if the MP time is slower than the system time, the MP time instantaneously passes forward. Thus, in reality, since a phone call of 3 minutes is reported as 3 minutes and 10 seconds, or a phone call of 10 minutes is reported as 8 minutes, the reliability of the metering which is closely related to the time management can not be secured.
Accordingly, the present invention is directed to a time management method for a switching system which obviates the problems and disadvantages in the conventional art.
An object of the present invention is to provide a time management method for a switching system that secures reliability of a system time management.
Another object of the present invention is to provide a time management method for a switching system that avoids time disconcordance due to an IPC delay.
Still another object of the present invention is to provide a time management for a switching system that secures reliability of an HW time.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a time management method for a switching system that periodically checks a failure state of an HW time using an OMDC in which an OMP sets an initial system time in accordance with the failure state of the HW time.
Also, to achieve the above objects of the present invention, there is provided a time management method for a switching system that computes an IPC delay by managing an RTC count value by each processor, and spontaneously sets and corrects a system time or an MP time by comparing the computed IPC delay with a time difference between an HW time and an OMP time or a time difference between the MP time and the OMP time.
Also, to achieve the above objects of the present invention, in a time management apparatus for a switching system provided with an OMP which is a master processor of a system time management, an OMDC which provides an HW time which is accessed by an HW time device to the OMP and an MP connected with the OMP, a time management method for a switching system include: periodically checking a failure state of an HW time using an OMDC; setting the HW time or a user time as an initial system time in accordance with the failure state of the HW time; resetting a system time by periodically comparing the HW time or an MP time, in which an IPC delay is considered, with an OMP time; requesting the initial system time to an OMP; setting an initial MP time as the received OMP time; and periodically comparing the MP time in which the IPC delay is considered with the OMP time and thereby resetting the MP time.